A Multi-channel Symbol Timing Recovery Architecture for 10GBASE-T System

A traditional symbol timing recovery architecture that used in 100BASE-T and 1000BASE-T is multi-phase selection based phase-locked loop (MPS-PLL). In 10GBASE-T system, the echo (ECHO) interference suppression requirement is much higher and hence the ECHO canceller is more sensitive to the timing jitter as well than that of 1000BASE-T system. Hence, the MPS-PLL architecture is difficult to implement in 10GBASE-T system. In this paper, we propose a hybrid symbol timing recovery (STR) architecture, which comprises a phase-locked loop (PLL) block accompanies three delay-locked loop (DLL) blocks as a four-channel STR system, and the corresponding finite state machine (FSM) control block that are suitable for 100BASE-T system. Finally, the complete simulation results, which include automatic gain control loop adaption, frequency offset estimation and correction, PLL phase and frequency recovery, DLL phase recovery, timing tracking, decision feedback equalizer training, echo canceller training and near end crosstalk canceller training in the training mode, show that the proposed four-channel STR architecture is practical.