An RF Receiver for Intra-Band Carrier Aggregation

Author

Sy-Chyuan Hwu ; Razavi, Behzad

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA

Volume

50

Issue

4

fYear

2015

fDate

Apr-15

Firstpage

946

Lastpage

961

Abstract

Carrier aggregation is an attractive approach to increasing the data rate in wireless communication. This paper describes an efficient carrier aggregation receiver architecture that employs one receive path and a single synthesizer. The block-downconversion scalable receiver translates all of the channels to the baseband and utilizes a new digital image rejection technique to reconstruct the signals. A receiver prototype realized in 45 nm CMOS technology along with an FPGA back end provides an image rejection ratio of at least 70 dB with a noise figure of 3.8 dB while consuming 15 mW.

Keywords

CMOS integrated circuits; field programmable gate arrays; image reconstruction; radio receivers; wireless channels; CMOS technology; FPGA back end; RF receiver architecture; block-downconversion scalable receiver; digital image rejection technique; image rejection ratio; intraband carrier aggregation; noise figure 3.8 dB; power 15 mW; signal reconstruction; size 45 nm; wireless communication; Bandwidth; Baseband; Gain; Mixers; Noise; Radio frequency; Receivers; Block downconversion; LTE; broadband LNA; carrier aggregation; image rejection;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2014.2386895

Filename

7029146