Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology

Systems-on-chip (SoCs) designed in ultra-deep sub-micron technologies (90nm and beyond) often comprise modules in multiple clock domains (MCD), which are usually interconnected using asynchronous interfaces. At the same time, in ultra-deep sub-micron (DSM) technologies, minimum width, spacing, inter-metal dielectric lengths are reduced, as well as distances between metal layers. These trends raise the coupling capacitance resulting in more severe crosstalks. Therefore, asynchronous interfaces may be subject to crosstalk in ultra-DSM technologies. In this paper, a quantitative investigation is performed to approximate the crosstalk effects in 90nm technology, and to compare them with effects in other DSM technologies. It is found that for wire lengths of 1mm, and more, crosstalk effects in a 90nm technology are substantially higher, about 1.3 times, than in a 180nm technology. Furthermore, three well known self-timed asynchronous design methods are analyzed with regards to crosstalk and the importance of coupling capacitances is established. It is shown that glitches can cause errors in self-timed designs. To our knowledge, this paper is the first to report crosstalk sensitivity in self-timed circuits, which are notably proposed as a solution to the timing problems found in advanced SoCs.