Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules

Author

Ye, Jhao-Ji ; Chen, You-Gang ; Wey, I-Chyn ; Wu, An-Yeu Andy

Author_Institution

Dept. of Electr. Eng., National Taiwan Univ., Taipei

fYear

2007

fDate

27-30 May 2007

Firstpage

869

Lastpage

872

Abstract

Data transmission on multiple clock domains faces reliable problems. The conventional globally asynchronous locally synchronous (GALS) technique can resolve the problem but has a high latency problem. In this paper, we present a novel asynchronous transmission technique called quasi-synchronous with an adaptive phase mechanism to reduce the transmission latency. Compared with the conventional GALS techniques, the proposed technique saves 50% ~ 83% of latency. It is implemented on standard-cell library by using TSMC 0.18 mum 1P6M CMOS technology

Keywords

CMOS digital integrated circuits; clocks; integrated circuit interconnections; system buses; 0.18 micron; TSMC 1P6M CMOS technology; adaptive phase mechanism; asynchronous transmission; data transmission; low-latency quasisynchronous transmission; multiple clock-domain IP modules; reduced transmission latency; CMOS technology; Circuits; Clocks; Delay; Flip-flops; Frequency; Metastasis; Synchronization; Transmitters; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378044

Filename

4252773