Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules

Data transmission on multiple clock domains faces reliable problems. The conventional globally asynchronous locally synchronous (GALS) technique can resolve the problem but has a high latency problem. In this paper, we present a novel asynchronous transmission technique called quasi-synchronous with an adaptive phase mechanism to reduce the transmission latency. Compared with the conventional GALS techniques, the proposed technique saves 50% ~ 83% of latency. It is implemented on standard-cell library by using TSMC 0.18 mum 1P6M CMOS technology