Low-latency Memory-efficient 150-Mbps Turbo FEC Encoder and Decoder

A high-speed turbo FEC code was proposed in the HomePlug AV standard for 200-Mbps high-data-rate home networking systems over power lines. In this paper, we demonstrate an efficient implementation of the FEC core to meet the high throughput requirement with lowered latency and lowered memory costs. The performance enhancement is achieved by combining radix-16 encoding with a time-shared conflict-avoidance memory access structure in the encoder, and by employing an optimized sub-bank parallel decoding architecture in the iterative decoder. A low-latency design can reduce the TX/RX turn-around time and the minimum inter-frame spacing required in a shared network, hence improving overall network utilization