Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees

Scaling of the on-chip feature size down into the deep submicron range has emphasized the importance of variations in interconnect delay due to capacitive coupling. A methodology for reducing crosstalk noise along tree-structured interconnects is proposed in this paper. An algorithm is implemented to compute the optimal sequence of shielding insertion along a capacitively coupled interconnect tree. The reduction in crosstalk is verified through simulation and compared to alternative shielding schemes, considering a limited availability of shielding resources. It is demonstrated that the proposed methodology consistently achieves greater reduction in interconnect delay variation.