Title :
Low-complexity Interpolation Architecture for Soft-decision Reed-Solomon Decoding
Author :
Zhang, Xinmiao ; Zhu, Jiangli
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH
Abstract :
Reed-Solomon (RS) codes have very broad applications in digital communication and storage systems. Among the decoding algorithms of RS codes, the Koetter-Vardy (KV) soft-decision decoding algorithm can achieve substantial coding gain with a polynomial complexity. One of the major steps of the KV algorithm is the interpolation. Recently, a new algorithm was proposed to solve the interpolation problem. Compared to previous efforts, this algorithm is computationally simpler, and thus can potentially lead to practical high-speed hardware implementations of the KV algorithm. This paper proposes novel transformation techniques to further reduce the hardware complexity of the new interpolation algorithm. In addition, efficient VLSI architectures are provided for the new algorithm
Keywords :
Reed-Solomon codes; VLSI; codecs; interpolation; logic circuits; Koetter-Vardy soft-decision decoding; Reed-Solomon codes; VLSI architectures; digital communication; digital storage systems; hardware implementations; low-complexity interpolation architecture; soft-decision Reed-Solomon decoding; Computer architecture; Electronic mail; Error correction codes; Field programmable gate arrays; Galois fields; Hardware; Interpolation; Iterative decoding; Reed-Solomon codes; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.378493
