LVDS Serial AER Link performance

Author

Miró-Amarante, L. ; Jiménez-Fernández, A. ; Linares-Barranco, A. ; Gómez-Rodríguez, F. ; Paz, R. ; Jimènez, G. ; Civit, A. ; Serrano-Gotarredona, R.

Author_Institution

Arquitectura y Tecnologia de Computadores, Univ. de Sevilla

fYear

2007

fDate

27-30 May 2007

Firstpage

1537

Lastpage

1540

Abstract

Address-event-representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The event information is transferred using a high speed digital parallel bus (typically 16 bits and 20ns-40ns per event). This paper presents a testing platform for AER systems that allows analysing a LVDS serial AER link produced by a Spartan 3 FPGA, or by a commercial LVDS transceiver. The interface allows up to 0.728 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that the platform could support 1.2 Gbps.

Keywords

VLSI; field programmable gate arrays; integrated circuit design; logic design; system buses; 0.728 Gbit/s; 1.2 Gbits/s; 16 bit; 20 to 40 ns; LVDS serial AER link performance; LVDS transceiver; Spartan 3 FPGA; VLSI chips; address-event-representation; asynchronous events transferring; bioinspired processing systems; communication protocol; complicated hierarchical structure; high speed digital parallel bus; Cables; Convolutional codes; Field programmable gate arrays; Magnetic noise; Noise cancellation; Pins; Protocols; Real time systems; Retina; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378704

Filename

4252944