Towards Automated Power Gating of Registers using CoDeL

In this paper, we use the CoDeL platform to develop test circuits and analyze the potential and performance impact of power gating individual registers. For each register, we examine the percentage of clock cycles for which they can be powered off, and the loss of performance incurred as a result of waiting for the power to be restored. Using a time-based technique to determine when the registers can be turned off results in 15% bit cycles saved at a performance loss of 2%. We then propose a method, which uses the information available to the CoDeL compiler to predict when the components can be powered off. Results show that our CoDeL assisted gating scheme allows up to 58% more power gated bit cycles than the time-based technique, with similar performance loss