DocumentCode
464873
Title
Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes
Author
Matús, Emil ; Tavares, Marcos B S ; Bimberg, Marcel ; Fettweis, Gerhard P.
Author_Institution
Vodafone Chair Mobile Commun. Syst., Technische Univ. Dresden
fYear
2007
fDate
27-30 May 2007
Firstpage
1657
Lastpage
1660
Abstract
We analyze the decoding algorithm for regular time-invariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which were used to design a novel low-complexity programmable decoder architecture with throughput in the range of 1 Gbit/s at moderate system clock frequencies. The synthesis results indicate that the decoder requires relatively small areas, even when high levels of parallelism are used.
Keywords
codecs; convolutional codes; parity check codes; programmable circuits; 3D signal processing scheme; LDPC convolutional codes; decoding algorithm; low density parity check codes; programmable decoder; Algorithm design and analysis; Clocks; Convolutional codes; Decoding; Frequency; Parity check codes; Signal analysis; Signal design; Signal processing algorithms; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.378838
Filename
4252974
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