Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications

This work proposes the usage of staggered initialization schemes in digital sequential circuits as complementary technique to reduce the simultaneous switching activity, pursuing the minimization of switching noise levels. Simultaneous switching noise (SSN) generation has been evaluated in digital sequential circuits during initialization and a general synthesis methodology has been proposed in order to implement the staggered initialization schemes at system level. The evaluation of this methodology was made with counter arrays using 0.35mum AMS library cells. In addition, timing considerations, clock suppression during initialization cycles, and the type of cell chosen to implement the staggered distribution are discussed. Main results include noise reduction levels, by suppression of power supply fluctuations, up to 66.7% in post-layout simulations when using staggered techniques enhanced with clock gating during initialization.