Noise-Aware Floorplanning for Fast Power Supply Network Design

As device size continues to shrink in the sub-micron regime, power supply noise is becoming a performance and reliability bottleneck in modern VLSI design. In this paper, we propose a new floorplanning methodology for fast power supply noise design convergence. By evaluating power supply noise at this early design stage, area-efficient floorplans with considering IR voltage drop and electromigration (EM) are generated. Compared to designs based on area-optimized floorplans, the proposed methodology achieves noise-satisfied designs with an average 52% less power routing resource.