A 3.7mW, 1.6V CMOS Analog Adaptive Equalizer for a 125Mbps Wire-Line Transceiver

Author

Fayed, Ayman ; Ismail, Mohammed

Author_Institution

Wireless Analog Technol. Center, Texas Instruments Inc., Dallas, TX

fYear

2007

fDate

27-30 May 2007

Firstpage

2136

Lastpage

2139

Abstract

An analog adaptive equalizer based on feed-forward architecture is implemented on 0.18mum digital CMOS process. The equalizer is implemented with only digital core devices and operates at 125Mbps over UTP CAT-5 cable of up to 100m length. Novel low-voltage, low-power circuit techniques resulted in 3.7mW total power consumption and supply voltage operation as low as 1.6V. This is over 3times power savings and 0.4V reduction in supply voltage from previously reported implementations on the same process node. The minimum horizontal eye opening of the equalizer (including the transmit path driver) under all cable length is 0.67 UI and the total area of the equalizer is 27738 mum².

Keywords

CMOS integrated circuits; adaptive equalisers; feedforward; low-power electronics; transceivers; 0.18 micron; 1.6 V; 125 Mbit/s; 3.7 mW; CMOS analog adaptive equalizer; UTP CAT-5 cable; digital CMOS process; feed-forward architecture; low-power circuit; low-voltage circuit; wire-line transceiver; Adaptive equalizers; CMOS process; Circuits; Energy consumption; Feedforward systems; Frequency response; Instruments; Intersymbol interference; Iron; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378595

Filename

4253093