On the Effectiveness of Reducing Large Linear Networks with Many Ports

Reduced order modeling is a well-known methodology for linear system modeling. In the past decade it has risen to prominence in the VLSI electronic design area as the de facto standard set of techniques for interconnect and package modeling. With shrinking technologies and faster operating frequencies, such previously ignored structures can have a first order influence in the behavior of many electronic systems. Reduced order modeling techniques can provide accurate, robust, accuracy-controlled models of linear networks. Unfortunately, most of these techniques have difficulty reducing networks with a large number of ports, such as power grids, substrate models and coupled data buses. In this paper we provide a characterization of this problem and discuss the complexity of several previously proposed techniques for handling this problem. We show that for most of these techniques there is little hope to expect that considerable reduction can be achieved. We also show that a simple, perhaps not obvious, approach can theoretically provide better reduction than most of the other techniques.