A Low Power Digital Signal Processor with Adaptive Band Activation for Digital Hearing Aid Chip

A low power digital signal processor (DSP) for a digital hearing aid chip is presented. The DSP integrates three programmable digital finite impulse response (FIR) filters. Each FIR filter can have one pass-frequency out of seven preset frequencies so that only three FIR filters can have the same flexibility as seven filters. Additionally, a silence mode is defined in which only one filter is activated. A digital voice activity detection circuit is implemented for this purpose. The DSP is implemented as part of a fully integrated digital hearing aid chip. It uses a 0.18 mum CMOS process and occupies an area of 0.5 mm₂. Power consumption is 25 muW in normal operating mode and 9 muW in silence mode at 0.9-V supply.