Title :
System-Level Design for Partially Reconfigurable Hardware
Author :
Qu, Yang ; Tiensyrjä, Kari ; Soininen, Juha-Pekka ; Nurmi, Jari
Author_Institution :
Commun. Platforms, Finland Tech. Res. Centre, Oulu
Abstract :
This paper presents a SystemC-based approach for system-level design of partially reconfigurable hardware. The main focuses are resource estimation to support system analysis, reconfiguration modeling for fast performance simulation, automatic generation of reconfigurable components and a static prefetch scheduler. The approach was applied in a real design case of a part of a WCDMA decoding algorithm on a commercial reconfigurable platform.
Keywords :
circuit simulation; code division multiple access; decoding; electronic design automation; high level synthesis; specification languages; SystemC-; WCDMA decoding algorithm; partially reconfigurable hardware; reconfigurable component automatic generation; reconfiguration modeling; resource estimation; static prefetch scheduler; system analysis; system-level design; Application specific integrated circuits; Delay; Design methodology; Field programmable gate arrays; Hardware; Performance analysis; Runtime; Silicon; Space technology; System-level design;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.378619
