Nonvolatile Flash Memories in Silicon-on-sapphire CMOS

Author

Yeh, Chun-Chen ; Culurciello, Eugenio

Author_Institution

Dept. of Electr. Eng., Yale Univ., New Haven, CT

fYear

2007

fDate

27-30 May 2007

Firstpage

2782

Lastpage

2785

Abstract

We designed, fabricated and tested four kinds of nonvolatile memories in a commercially-available 0.5mum silicon-on-sapphire CMOS process. The device tested are PMOS and NMOS with MOS- and MIM-based floating gates. We report on the test results of all four devices and demonstrate that MIM-based NMOS floating gate cells can be use to achieve a threshold shift of 0.4V and no significant decay of threshold voltage after small retentions tests of more than 100 s.

Keywords

CMOS memory circuits; MIM devices; flash memories; 0.4 V; 0.5 micron; 100 s; MIM-based floating gate; MOS-based floating gate; NMOS-based floating gate; PMOS-based floating gate; nonvolatile flash memory; silicon-on-sapphire CMOS; CMOS process; Character generation; Electrons; Flash memory; Flash memory cells; MOS devices; MOSFETs; Nonvolatile memory; Testing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378630

Filename

4253255

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=465025