A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264

H.264 and AVS are the two latest video coding standards. Since the similarity between their structures, it is feasible to develop a dual-mode VLSI decoder for supporting both standards, with substantially less cost than the solution with two individual decoders. In this paper, we propose a dual-standard VLSI architecture for MC interpolation, which is the most calculation intensive module of the dual-mode decoder. By applying reconfigurable FIR filters and an adaptive pipeline strategy, an implementation of the architecture can process realtime video streams in 1280times720, 30fps at low cost (11.5k gates, no RAM). This design also provides scalability to meet higher performance requirements.