Title :
Ultra Low Power CMOS PLL Clock Synthesizer for Wireless Sensor Nodes
Author :
Gundel, Adnan ; Carr, William N.
Author_Institution :
New Jersey Inst. of Technol., Newark, NJ
Abstract :
This paper describes the design of an ultra low power CMOS PLL clock synthesizer targeting wireless sensor applications that require low minimum power dissipation. Based on integer-N architecture, the PLL clock synthesizer produces a 100 kHz output signal from a reference input signal generated using an on-chip crystal oscillator operating at 32.768 kHz. Fabricated in a 0.6-mum N-well CMOS process technology, the PLL achieves a power consumption of 20 muW with a frequency accuracy of plusmn13 Hz.
Keywords :
CMOS integrated circuits; clocks; crystal oscillators; low-power electronics; phase locked loops; wireless sensor networks; 0.6 micron; 100 kHz; 20 muW; 32.768 kHz; CMOS PLL clock synthesizer; integer-N architecture; on-chip crystal oscillator; ultra low power; wireless sensor nodes; CMOS process; CMOS technology; Clocks; Oscillators; Phase locked loops; Power dissipation; Sensor phenomena and characterization; Signal generators; Synthesizers; Wireless sensor networks;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.378054
