Attaining Thermal Integrity in Nanometer Chips

As technology moves into the nanometer era, undesirable trends such as increasing power density, leakage power, and temperature variation within a chip have made thermal effects emerge as a major bottleneck for further technology scaling. Thermal effects are no longer just considered as a reliability issue, but it has also become a fundamentally important and comprehensive problem that includes timing and power issues as well. This paper first overviews the impact of thermal effects on power and performance. Two thermal-aware design techniques, area optimization and low-power cache design, are briefly described. The paper states that there is still plenty of room for further improvement in the area of thermal-aware design.