A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters

Digital sigma-delta (SigmaDelta) modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90nm CMOS digital low-pass SigmaDelta modulator, which has lower quantization noise and lower power consumption compared to other recent structures. A conventional digital SigmaDelta structure uses a 1-bit quantizer and generates very high quantization noise at higher frequencies. In this work, we present a low-pass digital SigmaDelta architecture with a multi-bit quantizer, which achieves very low in-band as well as out-of-band quantization noise levels. It is shown that the structure can be run at half the frequency while meeting the required noise performance and essentially delivering a better power-performance trade-off. The proposed architecture, along with the original 1-bit quantizer structure, has been synthesized in a 90nm CMOS process. Area and power consumption results are presented and a comparison between a commonly used structure and the proposed one is provided.