Analysis of Spurious Emission and In-Band Phase Noise of an All Digital Phase Locked Loop for RF Synthesis using a Frequency Discriminator

In almost every wireless RF application, a phase locked loop (PLL) is required. Digital signal processing especially for PLLs in CMOS technology is increasingly used instead of conventional analog processing to improve reliability, to reduce power consumption, and to allow for re-configurability. This paper presents a simulative analysis of an all digital PLL (ADPLL) with a two bit frequency discriminator (FD) in the feedback path. Effects on the in-band noise performance due to the sampling rate are treated. Furthermore, a theoretical prediction and simulative analysis of spurious emission offset frequencies will be given.