Fractional-Rate FM-to-Digital Δ-Σ Converters

Author

Cannillo, Francesco ; Toumazou, Christofer

Author_Institution

Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Medicine

fYear

2007

fDate

27-30 May 2007

Firstpage

3824

Lastpage

3827

Abstract

This paper presents novel fractional-rate architectures for FM-to-digital Δ-Σ modulation (FDSM) converters. The adoption of lower clock frequencies translates into reduction in power consumption. The general approach to fractional-rate FDSM architecture is introduced together with a novel two-flip-flop half-rate architecture reducing power consumption by 50%. System theory and supporting simulation results in the ST 90nm CMOS process are presented.

Keywords

Δ-Σ modulation; CMOS integrated circuits; flip-flops; frequency modulation; Δ-Σ modulation; 90 nm; CMOS process; FM-to-digital Δ-Σ converters; flip-flop half-rate architecture; fractional-rate architectures; power consumption; Biomedical engineering; Clocks; Digital modulation; Educational institutions; Energy consumption; Flip-flops; Frequency modulation; Low voltage; Phase modulation; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.377872

Filename

4253515

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=465193