A Sub-1V Low-Power High-Speed Static Frequency Divider

Author

Cheng, Kuo-Hsing ; Hung, Cheng-Liang ; Su, Chia-Wei

Author_Institution

Dept. of Electr. Eng., National Central Univ., Taoyuan

fYear

2007

fDate

27-30 May 2007

Firstpage

3848

Lastpage

3851

Abstract

In this paper, a low-power high-speed static frequency divider is proposed. By utilizing the forward body-bias (FBB) technique and parallel switching topology which employ differential PMOS input pair, the proposed 2:1 static frequency divider can not only be operated at a supply voltage of 0.7V but also keep the structure of tail current source to provide constant current. The frequency divider is designed based on TSMC 0.18mum 1p6m CMOS process. The 2:1 frequency divider can be operated up to maximum operating frequency 10.18 GHz while consuming 1.68 mW from a supply voltage of 0.9V. As operating at supply voltage of 0.7V, the operating frequency is 4.07GHz and the power dissipation is 0.96mW.

Keywords

CMOS integrated circuits; constant current sources; frequency dividers; 0.18 micron; 0.7 V; 0.9 V; 0.96 mW; 1.68 mW; CMOS process; PMOS input pair; forward body-bias technique; high-speed static frequency divider; parallel switching topology; CMOS logic circuits; Clocks; Frequency conversion; Latches; Low voltage; MOSFETs; Phase locked loops; Switches; Tail; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.377878

Filename

4253521