Title :
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization
Author :
Chiou, De-Shiuan ; Juan, Da-Cheng ; Chen, Yu-Ting ; Chang, Shih-Chieh
Author_Institution :
Nat. Tsing Hua Univ., Hsinchu
Abstract :
Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among maximum instantaneous current, IR drops and sleep transistor networks from a temporal viewpoint. Based on this relationship, we propose an algorithm to reduce the total sizes of sleep transistors in distributed sleep transistor network designs. On average, the proposed method can achieve 21% reduction in the sleep transistor size.
Keywords :
transistors; distributed sleep transistor network designs; fine-grained sleep transistor sizing algorithm; leakage power minimization; maximum instantaneous current; Algorithm design and analysis; CMOS logic circuits; CMOS technology; Clocks; Clustering algorithms; Leakage current; Microwave integrated circuits; Minimization methods; Permission; Sleep; Design; IR Drop; Leakage Current; Performance; Power Gating;
Conference_Titel :
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-59593-627-1
