Abstract :
In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent total leakage power of a large circuit block, considering Ijunc, sub-threshold leakage (Isub), and gate oxide leakage (Igate). We then propose our algorithm to estimate the full-chip leakage power with consideration of both Gaussian and non- Gaussian parameter distributions, capturing spatial correlations using a grid-based model. Experiments on ISCAS85 benchmarks demonstrate that the estimated results are very accurate and efficient. For a circuit with G gates, the complexity of our approach is O(G).
Keywords :
CMOS integrated circuits; Gaussian distribution; circuit complexity; integrated circuit design; leakage currents; statistical analysis; circuit block; circuit level; full-chip leakage power; gate oxide leakage; grid-based model; junction tunneling leakage; non-Gaussian parameter distributions; spatial correlations; statistical analysis; sub-threshold leakage; Algorithm design and analysis; CMOS technology; Circuits; Independent component analysis; Leakage current; MOS devices; Microelectronics; Principal component analysis; Statistical analysis; Tunneling; Algorithm; Design; Gaussian and non-Gaussian parameter distributions; Performance; Reliability; Statistical analysis; junction tunneling leakage;
