On-Chip Measurements Complementary to Design Flow for Integrity in SoCs

On-chip monitors are used in a dual role of dynamically monitoring the behavior of a die as well as verifying EDA tools for integrity in sub-100-nm CMOS SoC designs. This paper describes on-chip measurement techniques of supply noise, delay variation, substrate crosstalk, as well as inter- /intra-circuit operation interferences, along with their usage for verification/calibration of physical-level analysis methodologies. Silicon case studies include dynamic supply and delay variability as well as analog signal deterioration evaluated in 90-nm/180-nm chips.