DocumentCode
465320
Title
Synchronous Elastic Circuits with Early Evaluation and Token Counterflow
Author
Cortadella, Jordi ; Kishinevsky, Mike
Author_Institution
Univ. Polytech. de Catalunya, Barcelona
fYear
2007
fDate
4-8 June 2007
Firstpage
416
Lastpage
419
Abstract
A protocol for latency-insensitive design with early evaluation is presented. The protocol is based on a symmetric view of the system in which tokens carrying information move in the forward direction and anti-tokens canceling information move in the backward direction. An implementation of the protocol and an example illustrate the flow for converting a regular synchronous design into an elastic circuit with early evaluation.
Keywords
network synthesis; anti-tokens canceling information; latency-insensitive design; protocol; synchronous elastic circuits; token counterflow; Asynchronous circuits; Circuit synthesis; Delay; Design automation; Logic; Multiplexing; Performance analysis; Petri nets; Protocols; System performance; Design; Elastic designs; Theory; Verification; protocols; synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Conference_Location
San Diego, CA
ISSN
0738-100X
Print_ISBN
978-1-59593-627-1
Type
conf
Filename
4261218
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