Accelerating Harmonic Balance Simulation Using Efficient Parallelizable Hierarchical Preconditioning

An efficient parallelizable hierarchical preconditioning framework is proposed to accelerate the simulation of analog and RF circuits using harmonic balance (HB). We show that the proposed hierarchical preconditioning scheme not only brings significant runtime speedup over the conventional block diagonal (BD) preconditioner for driven circuits, but also enhances the simulation of autonomous circuits. Due to the specific algorithm construction, this hierarchical preconditioning can be achieved by solving a set of linear matrix problems with tree-like data dependency. Hence, it can be naturally parallelized to further improve the simulation efficiency. An efficient parallel HB simulation engine has been developed by distributing the simulation workload over a cluster of machines via message passing interface (MPI). Our experiments have shown that this new parallel HB algorithm can achieve the significant runtime speedup over the conventional serial preconditioning technique.