Extraction of Statistical Timing Profiles Using Test Data

Systematic variations with device parameters and critical dimensions are crucial information in achieving higher yields with semiconductor devices. In this paper, we propose a method to extract systematic variation models of segment delays based on the measured path delays of tested chips. First, we cluster chips according to the similarity of the path delay vectors. Then, for each cluster, a hierarchical variation model is built. The extracted models are closely related to the design and can have many potential applications for yield and quality enhancements.