An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires

Higher-than-normal wire temperatures and temperature gradients between the sending and receiving ends of a wire that are caused due to Joule heating and substrate hotspots affect the propagation delay of a wire significantly. In this paper, we develop a high-level model to track wire temperatures and delay variability during early stage design exploration. Results using our model show that ALU result bus wires in a 4-issue processor are likely to reach temperatures as high as 103degC (117degC) in 130-nm (45-nm) technology which is greater than the 100deg C maximum normally assumed during interconnect design. For a 130-nm processor with no power and thermal management, the temperature-induced timing violations in the ALU result bus, on average across ten SPEC CPU2K benchmarks, is 2.27 per hundred bus references and it can be as high as 4.91 per hundred bus references in some programs. It increases to an average of 6.20 per hundred bus references for the same processor at the 45-nm technology node.