DocumentCode :
465350
Title :
EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure
Author :
Deng, Shujun ; Bian, Jinian ; Wu, Weimin ; Yang, Xiaoqing ; Zhao, Yanni
Author_Institution :
Tsinghua Univ., Beijing
fYear :
2007
fDate :
4-8 June 2007
Firstpage :
588
Lastpage :
593
Abstract :
This paper presents an efficient algorithm to solve the satisfiability (SAT) problem for RTL designs using a complete hybrid branch-and-bound strategy with conflict-driven learning. The main framework is the extended Davis-Putnam-Logemann-Loveland procedure (DPLL) which is a unified procedure combining Boolean logic and arithmetic operations. A hybrid two- literal-watching scheme and interval reasoning based on RTL predicates are used as the powerful hybrid constraint propagation strategies. Conflict-based learning is also implemented as another important technique to enhance efficiency. Comparisons with a state-of-the-art RTL SAT solver, a SMT solver and an ILP solver show that EHSAT outperforms these solvers for RTL satisfiability problems.
Keywords :
arithmetic; computability; inference mechanisms; learning systems; tree searching; Boolean logic; Davis-Putnam-Logemann-Loveland procedure; arithmetic operations; conflict-based learning; conflict-driven learning; hybrid branch-and-bound strategy; hybrid two-literal-watching scheme; interval reasoning; satisfiability solver; Algorithm design and analysis; Arithmetic; Artificial intelligence; Boolean functions; Electronic design automation and methodology; Formal verification; Logic circuits; Logic programming; Permission; Surface-mount technology; Algorithms; Satisfiability; Verification; conflict analysis; constraint propagation; design verification;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Conference_Location :
San Diego, CA
ISSN :
0738-100X
Print_ISBN :
978-1-59593-627-1
Type :
conf
Filename :
4261251
Link To Document :
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