Abstract :
This paper presents the many-core architecture, with hundreds to thousands of small cores, to deliver unprecedented compute performance in an affordable power envelope. We discuss fine grain power management, memory bandwidth, on die networks, and system resiliency for the many-core system.
Keywords :
transistors; die networks; fine grain power management; many-core architecture; memory bandwidth; system resiliency; transistor; CMOS logic circuits; CMOS technology; Computer architecture; Logic arrays; Logic design; Microarchitecture; Multimedia systems; Permission; Power system reliability; Transistors; CMOS; Design; Memory; Performance; Power; Reliability; Variability;
