DocumentCode :
465401
Title :
A Framework for the Validation of Processor Architecture Compliance
Author :
Adir, Allon ; Asaf, Sigal ; Fournier, Laurent ; Jaeger, Itai ; Peled, Ofer
Author_Institution :
IBM, Haifa
fYear :
2007
fDate :
4-8 June 2007
Firstpage :
902
Lastpage :
905
Abstract :
We present a framework for validating the compliance of a design with a given architecture. Our approach is centered on the concept of misinterpretations. These include missing behavior, wrong understanding of a behavior, or confusion with similar behavior described in the architecture or elsewhere. We formally capture the architecture behavior in the form of flowcharts and automatically derive a list of architecture misinterpretations from these flowcharts. These misinterpretations constitute the backbone of coverage models targeted by a suite of tests. The suite is automatically generated by a model-based test case generator. A compliance validation system based on these principles has been developed and used in two actual industrial processes of checking compliance with the PowerPC architecture.
Keywords :
microprocessor chips; PowerPC architecture; compliance validation system; flowcharts; processor architecture; Automatic testing; Computer bugs; Flowcharts; Logic design; Permission; Power system modeling; Process design; Spine; Standardization; System-on-a-chip; Compliance suite; Conformance; Experimentation; Processor verification; Standardization; Verification;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Conference_Location :
San Diego, CA
ISSN :
0738-100X
Print_ISBN :
978-1-59593-627-1
Type :
conf
Filename :
4261311
Link To Document :
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