Title :
Design and Synthesis of Flagged Binary Adders with Constant Addition
Author :
Dave, Vibhuti ; Oruklu, Erdal ; Saniie, Jafar
Author_Institution :
Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, Illinois, USA. vdave@ece.iit.edu
Abstract :
Multi-operand addition is utilized in various applications like, multiplication, convolution and several image processing algorithms such as filtering. Various adder architectures have been proposed to accomplish the addition of more than two operands, consuming minimum delay and area. Recently, a new technique called flagged prefix addition has been proposed that utilizes prefix tree adders to perform increment and decrement operations by generating flag bits. An extension to this adder has also been proposed enhancing the functionality of the same to allow the addition of any arbitrary number, thereby accomplishing multi-operand addition. This paper extends the idea of generating the flag bits to the carry-skip and the carry-select adders. A thorough evaluation has been performed to analyze the performance of the carry-select, carry-skip, and the prefix tree architectures incorporating the new design in terms of power, area, and delay.
Keywords :
Adders; Algorithm design and analysis; Application software; Computer architecture; Convolution; Delay; Filtering algorithms; Image processing; Signal generators; Signal processing algorithms; Binary Addition; Constant Addition; Flagged Addition; Prefix Computation;
Conference_Titel :
Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on
Conference_Location :
San Juan, PR
Print_ISBN :
1-4244-0172-0
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2006.381985