High Performance Memory Read Using Cross-Coupled Pull-up Circuitry

A novel design for decreasing energy and delay during the read cycle of a standard six-transistor differential SRAM cell is presented in this paper. Removal of the pre- charge transistors from the bit-lines of the SRAM reduces energy consumption. This also eliminates the need for a pre- charge phase which decreases the total delay of a read cycle. Additional logic to improve the speed of a read and to ensure that the bit-lines retain a sufficient voltage difference is placed just before the output on the bit-lines. This is especially significant in the design of pipelined memories where the delay per stage is determined by the time it takes to read a value from a cell as opposed to decoding an address or generating the output of the SRAM. Circuit simulations in 180-nm CMOS show a decline in energy consumption by a minimum of 9.2% and up to 98.6%. Worst case delay is reduced by 27.6%. The following paper explains the proposed read logic in detail, describes the techniques used for the analysis, and compares the results with the standard method for fast, low-power read accesses.