A Rail-to-Rail Delay Line for Time Analog-to-Digital Converters

This paper presents a rail-to-rail, voltage-to-time conversion circuit, which can be used in time-analog-to-digital (TAD) converters. The building block of TAD converters is a number of cascaded inverters, called a delay line. A pulse signal is applied to input of very first inverter of the delay line while an input signal to be digitized is applied to the positive supply terminal (PST) of a delay line. By this way, an input signal, in reality, behaves like a positive supply voltage. This will introduce a variable clock-edge-delay at the output of a delay line defined by the input signal at positive supply terminal. On the other hand, functionality of this earlier method is limited since input signal can not be lower than the threshold voltage of MOS devices in a basic inverter cell. This limitation comes from the fact that full signal range is not possible. Hence, a new architecture is proposed, which basically consists of two sets of delay lines, where an input signal is connected to a positive supply terminal (Vdd) in one set and it is connected to negative supply terminal (Vgnd) in the other set. In this paper, there is also simple digital logic circuit is shown to combine outputs of two sets. Hence, full signal-swing from Vgnd to Vdd can be converted to digital without any significant dead regions.