A Delay Characterization Method for Integrated Devices

We present in this paper a new approach for on-chip delay characterization of integrated passive and active devices such as transistors, interconnects and analog resistors and capacitors. The proposed method is a time-domain technique that uses on-chip configurable ring oscillators to characterize independently dynamic parasitic resistance and capacitance of the device under characterization. With the use of empirical techniques, based on interpolated look-up tables of pre-simulated data, the method achieves very good estimates of capacitance and resistance. A calibration technique to compensate process variations is also proposed and validated. The proposed method is implemented on a chip, designed in the CMOS 180nm TSMC technology. The chip was manufactured and is currently under verification.