An Ultra-Low Power Pulse-Based UWB Transceiver SoC with on-Chip ADC

Ultra-low power is desirable in wireless mobile communications. This paper presents design of an ultra-low power, pulse-based, non-carrier, ultra wideband (UWB) transceiver system-on-a-chip (SoC) with on-chip analog-to-digital converter (ADC) for high payload wireless video/audio/multimedia streaming applications. A novel global power switching technique is used to reduce the UWB SoC power dissipation. The UWB SoC adopts a single-band (7.5GHz from 3.1GHz to 10.6GHz), pulse-based non-carrier architecture, which consists of pulse generator, low-noise amplifier (LNA), correlator, integrator, timing controller and on-chip ADC. The SoC features BPSK modulation and Gaussian pulsing. Simulation shows that the global power switching technique can save up to 95% power at 100Mbps and up to 70% power at 1Gbps for the UWB SoC without serious performance degradation. The UWB SoC performance is satisfactory as following: LNA features NF<3dB and gain of 10dB; pulse generator features pulse width of 50ps; correlator features NF<4dB and conversion gain of 0.6dB; ADC features 10b, 500Msps, INL of 0.8LSB, DNL of 0.5LSB and SINAD of 57dB; and total power is only 136.53mW at 100Mbps. The UWB SoC is designed in IBM 0.18¿m CMOS.