DocumentCode
466411
Title
Automatic generation of transaction level models for rapid design space exploration
Author
Peng, Junyu ; Gerstlauer, Andreas ; Gajski, Daniel D. ; Dömer, Rainer ; Shin, Dongwan
Author_Institution
Univ. of California Irvine, Irvine
fYear
2006
fDate
22-25 Oct. 2006
Firstpage
64
Lastpage
69
Abstract
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate such transaction-level models from abstract input descriptions. Designers have to write such models manually, which is a tedious and error-prone task, and one of bottlenecks in improving designer´s productivity. In this paper, we propose a method to generate transaction-level models from virtual architecture models where components communicate via abstract message-passing channels. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Experimental results show that significant productivity gains can be achieved, demonstrating the effectiveness and benefits of our approach for rapid, early exploration of communication design space.
Keywords
logic CAD; message passing; system-on-chip; transaction processing; abstract input descriptions; abstract message-passing channels; automatic generation; rapid design space exploration; transaction-level models; virtual architecture models; Computational modeling; Computer simulation; Concrete; Design automation; Embedded computing; Permission; Productivity; Space exploration; System-level design; System-on-a-chip; communication synthesis; transaction-level model;
fLanguage
English
Publisher
ieee
Conference_Titel
Hardware/Software Codesign and System Synthesis, 2006. CODES+ISSS '06. Proceedings of the 4th International Conference
Conference_Location
Seoul
Print_ISBN
1-59593-370-0
Electronic_ISBN
1-59593-370-0
Type
conf
DOI
10.1145/1176254.1176272
Filename
4278492
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