DocumentCode :
46655
Title :
Self-Rectifying Twin-Bit RRAM in 3-D Interweaved Cross-Point Array
Author :
Shu-En Chen ; Yung-Wen Chin ; Min-Che Hsieh ; Chu-Feng Liao ; Tzong-Sheng Chang ; Chrong-Jung Lin ; Ya-Chin King
Author_Institution :
Inst. of Electron. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume :
3
Issue :
4
fYear :
2015
fDate :
Jul-15
Firstpage :
336
Lastpage :
340
Abstract :
A new self-rectifying twin-bit RRAM in a novel 3-D interweaved cross-point array has been proposed and demonstrated in 28-nm high-k metal gate CMOS back end of line (BEOL) process. This high density of array architecture with the cell size only 70 × 100 × 187 nm can be manufactured without additional mask or process. The RRAM film is formed by via plug over shifting between two metal lines in back-end process with TaN/TaOxN RRAMs on both sides of a single via. The BEOL RRAM shows large read window between states. Fast switching time of 1 us for set operation and 10 us for reset was demonstrated. Excellent selectivity by its asymmetric IV characteristic enables the twin-bit 1R cells to be efficiently stacked in 3-D cross-point arrays without select transistors.
Keywords :
CMOS memory circuits; rectifiers; resistive RAM; tantalum compounds; 3-D interweaved cross-point array; BEOL process; TaN; TaOxN; asymmetric IV characteristic; back end of line process; complementary metal oxide semiconductor; high-k metal gate CMOS; resistive random-access memory; self-rectifying twin-bit RRAM; size 28 nm; switching time; twin-bit 1R cell; Arrays; CMOS integrated circuits; Metals; Microprocessors; System-on-chip; Three-dimensional displays; Back end of line process (BEOL); Lateral via resistive RAM (LVRRAM); embedded memory self-rectifying RRAM; nonvolatile memory (NVM);
fLanguage :
English
Journal_Title :
Electron Devices Society, IEEE Journal of the
Publisher :
ieee
ISSN :
2168-6734
Type :
jour
DOI :
10.1109/JEDS.2015.2425652
Filename :
7096920
Link To Document :
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