Development of a Deep-Submicron CMOS Process for Fabrication of High Performance 0.25 μm Transistors

A process for fabrication of 0.25 mum CMOS transistors has been demonstrated. NMOS transistors with drain current of 177 muA/mum at VG=VD=2.5 V and a PMOS transistors with drain current of 131 muA/mum at VG=VD=-2.5 V are reported. The threshold voltages are 1.0 V for the NMOS and -0.735 V for the PMOS transistors. The mask defined gate lengths are 0.5 mum and 0.6 mum for the NMOS and PMOS, respectively. Through a photoresist trimming process, the poly gate lengths are 0.25 mum and 0.35 mum or smaller. Electrical extraction of the gate lengths should yield effective gate lengths of 0.25 mum or smaller. These are the smallest transistors ever fabricated in the SMFL at RIT. Large off-state leakage is reported for the NMOS due to drain leakage induced by implant damage or aggressive titanium silicide formation. A better understanding of this leakage is being investigated and process recommendations given.