DocumentCode :
467152
Title :
A New Memory-Based Systolic Algorithm for DST with Low Hardware Complexity
Author :
Chiper, D.F.
Author_Institution :
Tech. Univ. Gh. Asachi Iasi, Iasi
Volume :
1
fYear :
2007
fDate :
13-14 July 2007
Firstpage :
1
Lastpage :
4
Abstract :
In this paper a new memory-based VLSI algorithm for 1D-DST is proposed. This algorithm uses a new formulation of the DST into cyclic convolution forms that uses a new input restructuring sequence. This approach significantly reduces the overheads necessary to restructure the DST into cyclic convolution structures. We can further use this appropriate reformulation of the DST to map it onto a linear systolic array with high through-put and low I/O cost. The systolic array that can be obtained has a high degree of modularity and regularity with only local interconnections.
Keywords :
Karhunen-Loeve transforms; VLSI; circuit complexity; coprocessors; memory architecture; systolic arrays; transform coding; video coding; 1D-DST; cyclic convolution; input restructuring sequence; linear systolic array; low hardware complexity; memory-based VLSI algorithm; memory-based systolic algorithm; Convolution; Costs; Discrete cosine transforms; HDTV; Hardware; Kernel; Signal processing algorithms; Systolic arrays; Very large scale integration; Video compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Circuits and Systems, 2007. ISSCS 2007. International Symposium on
Conference_Location :
Iasi
Print_ISBN :
1-4244-0969-1
Electronic_ISBN :
1-4244-0969-1
Type :
conf
DOI :
10.1109/ISSCS.2007.4292682
Filename :
4292682
Link To Document :
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