• DocumentCode
    467553
  • Title

    Backlog Aware Low Complexity Schedulers for Input Queued Packet Switches

  • Author

    Dua, Aditya ; Bambos, Nicholas ; Olesinski, Wladek ; Eberle, Hans ; Gura, Nils

  • Author_Institution
    Stanford Univ., Stanford
  • fYear
    2007
  • fDate
    22-24 Aug. 2007
  • Firstpage
    39
  • Lastpage
    46
  • Abstract
    We study the problem of packet scheduling in input queued packet switches, with an emphasis on low complexity and ease of implementation. Toward this end, we propose a class of subset based schedulers, wherein an N x N switch is operated using only a small set of N configurations in every time-slot. We show that the performance of subset based scheduling is comparable to that of the benchmark maximum weight matching (MWM) scheduler, albeit at much lower complexity. Next, we relate subset based scheduling to the well known wrapped wavefront arbiter (WWFA) [14] and propose BA-WWFA, a backlog aware version of WWFA. The BA-WWFA scheduler significantly enhances the performance of WWFA, while retaining its ease of hardware implementation. The performance gains are especially noteworthy under non-uniform loading of the switch. Given their ease of implementation and MWM like performance, the schedulers proposed in this paper represent an attractive option for high performance packet switching.
  • Keywords
    packet switching; queueing theory; backlog aware low complexity schedulers; input queued packet switches; maximum weight matching scheduler; wrapped wavefront arbiter; Bandwidth; Computational complexity; Delay; Hardware; Packet switching; Processor scheduling; Robust stability; Scheduling algorithm; Switches; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Performance Interconnects, 2007. HOTI 2007. 15th Annual IEEE Symposium on
  • Conference_Location
    Stanford, CA
  • ISSN
    1550-4794
  • Print_ISBN
    978-0-7695-2979-0
  • Type

    conf

  • DOI
    10.1109/HOTI.2007.4
  • Filename
    4296806