Title :
FPGA/DSP-based Configurable Multi-Channel Counter
Author :
Audino, D. ; Baronti, F. ; Lazzeri, A. ; Roncella, R. ; Saletti, R.
Author_Institution :
Dip. Eng. dell Informazione, Univ. di Pisa, Pisa, Italy
Abstract :
In this paper we present a high-performance configurable multi-channel counter, suitable for many scientific applications. The counter array features 64 input channels, is able to acquire incoming events with a pulse rate up to 45 MHz, and provides an integration window (time resolution) down to 24 mus with a 32 b counting depth. Moreover, the time resolution reaches the value of 8 mus with a 8b counting depth and 1 mus if only 8 channels are used. The collected data are both real-time processed and transmitted over a high-speed IEEE 1394 serial link. The same link is used to remotely set up and control the entire acquisition process, thus giving the system a high degree of flexibility. A small-sized and low-cost implementation is obtained with a Commercial-Off-The-Shelf FPGA/DSP-based single board. A theoretical model that immediately gives the system performance is presented. Finally, we describe the system functional test, the results of which are in good accordance with those derived from the model.
Keywords :
counting circuits; digital signal processing chips; field programmable gate arrays; logic testing; microcontrollers; system buses; DSP-based single board; commercial-off-the-shelf FPGA; configurable multichannel counter; data acquisition process; high-speed IEEE 1394 serial link; integration window; system functional test; time resolution; Control systems; Counting circuits; Digital signal processing; Field programmable gate arrays; Filtering; Instruments; Real time systems; System performance; System testing; Time measurement;
Conference_Titel :
Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on
Conference_Location :
Lubeck
Print_ISBN :
978-0-7695-2978-3
DOI :
10.1109/DSD.2007.4341495