• DocumentCode
    4685
  • Title

    Efficient Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Geometric Reduction

  • Author

    Chih-Hung Liu ; Chun-Xun Lin ; I-Che Chen ; Lee, D.T. ; Ting-Chi Wang

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Bonn, Bonn, Germany
  • Volume
    33
  • Issue
    12
  • fYear
    2014
  • fDate
    Dec. 2014
  • Firstpage
    1928
  • Lastpage
    1941
  • Abstract
    Given a set of pin-vertices, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects all the pin-vertices possibly through Steiner points using vertical and horizontal segments with the minimal wirelength and without intersecting any obstacle. To deal with multiple routing layers and preferred routing orientations, we consider the multilayer obstacle-avoiding rectilinear Steiner minimal tree (ML-OARSMT) problem and the obstacle-avoiding preferred direction Steiner tree (OAPD-ST) problem. First, we prove that the multilayer case is theoretically different from the 2D one, and propose a reduction to transform a multilayer instance into a 3D instance. Based on the reduction, we apply computational geometry techniques to develop an efficient algorithm, utilizing existing OARSMT heuristics, for the ML-OARSMT problem and the OAPD-ST problem. Furthermore, we develop an advanced Steiner point selection to avoid inferior Steiner points and to improve the solution quality. Experimental results show that our algorithm provides a solution with excellent quality and has a significant speed-up compared to previously known results.
  • Keywords
    VLSI; computational geometry; integrated circuit design; trees (mathematics); 2D instance; 3D instance; ML-OARSMT problem; OAPD-ST problem; OARSMT heuristics; VLSI layout design; advanced Steiner point selection; computational geometry techniques; geometric reduction; horizontal segments; inferior Steiner points; minimal wirelength; multilayer obstacle-avoiding rectilinear Steiner miniminal tree construction; multiple routing layers; obstacle-avoiding preferred direction Steiner tree problem; orientations; pin-vertices; routing orientations; vertical segments; very large scale integration layout design; Algorithm design and analysis; Computational geometry; Integrated circuits; Routing; Steiner trees; Obstacle-Avoidance; Obstacle-avoidance; Physical Design; Rectilinear Steiner Minimal Tree (RSMT); Routing; physical design; rectilinear Steiner minimal tree (RSMT); routing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2014.2363390
  • Filename
    6930811