DocumentCode :
469217
Title :
A New Fast Architecture for HD H.264 CAVLC Multi-syntax Decoder and its FPGA Implementation
Author :
George, Tony Gladvin ; Malmurugan, N.
Volume :
3
fYear :
2007
fDate :
13-15 Dec. 2007
Firstpage :
118
Lastpage :
122
Abstract :
In this paper, we present a fast architecture of real-time CAVLC decoder (CAVLD) implemented in a FPGA. The real-time performance is achieved by exploring the pipelining possibilities between the sub-modules and multi syntax decoding. The implemented fast CAVLD architecture, when integrated with H264 decoder was capable of parsing at 30fps for 1080p streams for an encoded bit stream at a bit rate of 200 Mbps to achieve the real-time performance, while the clock is operated at 74.25 MHz. The result numbers of ALUs are 3266 and the critical path is within 10.5ns
Keywords :
Clocks; Computational intelligence; Computer architecture; Field programmable gate arrays; Hardware; High definition video; Iterative decoding; Pipelines; Throughput; Video compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Conference on Computational Intelligence and Multimedia Applications, 2007. International Conference on
Conference_Location :
Sivakasi, Tamil Nadu
Print_ISBN :
0-7695-3050-8
Type :
conf
DOI :
10.1109/ICCIMA.2007.335
Filename :
4426352
Link To Document :
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