Neural Network Based Macromodels for High Level Power Estimation

In this article, a neural network based macromodeling technique is proposed for high level power estimation of logic circuits. With the advent of high-density microelectronic devices, power dissipation of VLSI circuits has become a critical concern. Consequently power estimation accuracy at higher levels is an important issue to avoid costly redesign steps. Artificial Neural Network (ANN) with its capability to derive some meaning from complicated or imprecise data has been exploited for this purpose. A simple Back Propagation (BP) algorithm is employed to train a feed-forward neural network with the available data set to find out the weights and biases of the interconnecting layers, and subsequently the neural network is used as a model to determine the power dissipation for test inputs. The experimental results have been compared with that of the previous approaches and accordingly it establishes the effectiveness of the proposed approach for high level power estimation.