Performance Analysis of DVS Algorithms for Reducing Processor Energy Consumption

Dynamic voltage scaling (DVS) is an energy saving technique, which is achieved by reducing energy dissipation of the core by lowering the supply voltage and operating frequency. DVS technology lies at the heart of advanced digital products ranging from laptops, personal digital assistants, mobile phones and even game consoles. DVS has been widely acknowledged as a powerful technique for trading off for power consumption and delay for processors. In this paper a new DVS algorithm is presented, which achieves better energy savings with deadline guarantees by splitting task between discrete frequency levels and task deferring technique. The proposed DVS algorithm is compared with existing basic RT-DVS algorithms for real-time periodic task sets, analyzing their energy efficiency, and discussing the performance differences quantitatively. The simulation results show that the proposed algorithm closely approaches the theoretical lower bond on energy consumption and reduces the energy consumption by 10-15% over the existing DVS algorithm.