Custom 14-Bit, 125MHz ADC/Data Processing Module for the KL Experiment at J-Parc

We present a custom 16-channel ADC/data processing module, designed for a high energy physics kaon experiment at JPARC (Japan particle accelerator research complex). This Board will receive signals from the cesium iodide (Csl) calorimeter, and will be one of the two ADC modules in the experiment´s DAQ system. Each analog PMT pulse is amplified and passed through a 10-pole filter/shaper, before being applied to a 14-Bit, 125MHz sample-and-hold ADC chip. Sampling for all 3,200 calorimeter channels is simultaneous on one low jitter system clock. Data are then processed locally with field programmable gate arrays (FPGAs) that perform the board total energy calculation and determine real-time energy related values for the system trigger supervisor. These values are presented in both parallel and serialized formats on the front panel. The module is provided with a pipeline, up to 25us (3,200 samples) long, which stores the acquisitions, awaiting the system trigger pulse. After a trigger, data are packed and buffered for readout. The readout can be performed via the VME32/64 backplane, or via the front panel optical link.